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曾益慧创杯 · Team LDO project · 2026

From schematic to post-layout evaluation

A 1.8 V CMOS LDO team project in SMIC 180 nm. My work included selected schematic analysis, PVT/PSRR/STB simulation, layout and Calibre practice, post-layout evaluation, and regional hardware tasks.

SMIC 180 nmPVT / PSRR / STBCalibre DRC / LVS / PEXLabVIEW ATE
≈126 mV
reported dropout
67.9-74.5°
post-layout phase margin
65.9-69.3 dB
PSRR at 1 kHz
Three-stage LDO concept: a classic PMOS feedback loop for preliminary design; parallel semi-discrete pass branches for the regional final; a LabVIEW dataflow interface and instruments for national-final test preparation.
Preliminary → Regional Final → National FinalView full concept ↗

AI-generated conceptual overview, not the team's implementation schematic or measurement data. The LabVIEW interface illustrates national-final test preparation, not a completed or executable test system.

Project path

Four connected tasks

  1. 01

    Team design & simulation

    1.8 V CMOS LDO

    Architecture review and eight dedicated simulation benches in SMIC 180 nm.
  2. 02

    Physical workflow

    Layout, LVS, PEX, post-layout

    Layout, LVS, parasitic extraction, and post-layout evaluation.
  3. 03

    Team hardware task

    Regional semi-discrete LDO

    A separate 25 V-to-12 V BJT regulator built and debugged at the regional final.
  4. 04

    Preparation record

    National-stage automated testing

    LabVIEW/IECUBE preparation for instrument control, scans, logging, and safe recovery.
01 · Architecture

1.8 V CMOS LDO architecture

The team design targets a 1.8 V output from a 3-5 V supply in a 0.18 µm CMOS process. A bandgap-derived reference, feedback network, error amplifier, bias network, common-source driver, and PMOS pass device close the regulation loop around a 1 µF external output capacitor. The error amplifier uses a PMOS-input folded-cascode first stage followed by a common-source stage.

  1. ReferenceBandgap core

    ≈1.2 V reference

  2. Error sensingPMOS-input folded cascode

    Compares feedback with the reference

  3. Gate driveCommon-source stage

    Drives the large PMOS gate

  4. Power pathPMOS pass device

    Regulates current from VIN to VOUT

  5. FeedbackResistor network

    Returns a scaled VOUT to the amplifier

Cadence transistor-level schematic of the team 1.8 V SMIC 180 nm LDO, including its reference, error-amplifier, feedback, bias, and PMOS pass-device paths.
Team top-level transistor schematicReference, amplifier, feedback, bias, and PMOS pass-device paths.
Process
0.18 µm CMOS

SMIC design environment

Operating envelope
VIN 3-5 V · VOUT 1.8 V

1 µF external output capacitor

Temperature
-40 / 27 / 85 °C

TT, FF, SS, FS, and SF report labels

Core checks
DC · regulation · Iq

PSRR · dropout · stability

02 · Simulation

Eight dedicated testbenches

Separate ADE environments cover operating point, accuracy, line/load regulation, dropout, quiescent current, PSRR, and loop stability. The report uses TT/FF/SS/FS/SF labels; some archived state names still need mapping before a clean rerun.

  1. 01SIM_LDO_BASIC_DC

    Operating point and transistor headroom

  2. 02SIM_LDO_ACCURACY

    Output error under the declared point set

  3. 03SIM_LDO_LINEAR

    VIN sweep and line-regulation extraction

  4. 04SIM_LDO_LOADING

    Load sweep and load-regulation extraction

  5. 05SIM_LDO_DROPOUT

    VIN threshold search against the output limit

  6. 06SIM_LDO_CURRENT

    Quiescent-current evaluation

  7. 07SIM_LDO_PSRR

    Supply-ripple rejection at declared frequencies

  8. 08SIM_LDO_STB

    Loop gain, phase margin, and gain margin

03 · Results

Post-layout results and remaining gaps

MetricReported resultAssessment
Output accuracyPartial closure1.7893-1.8186 V in the accuracy table; the line sweep reaches about 1.8310 V.Typical/base point supported; the full-envelope ±1% target is not closed.
Load regulationRerun needed0.312 mV pre-layout PVT worst case; no recovered post-layout raw point table.Promising, but a clean post-layout rerun is still needed.
Line regulationOpen gapAbout 12.5 mV across VIN = 3-5 V at the visible SS/85 °C worst case.Open gap against the ≤3 mV base target.
Quiescent currentBase supported8.745-9.173 µA at the reported base-condition load.Meets the ≤10 µA base target; the advanced condition is not supported.
PSRRBase supported65.91-69.27 dB at 1 kHz in the post-layout report.Meets the >60 dB base target; broadband >70 dB is not closed.
DropoutReport-backedApproximately 126 mV in the report; worst marked VIN is near 1.926 V.Within the ≤200 mV base target; raw PEX outputs are missing.
Loop stabilityArchive-supported67.92-74.54° phase margin and 21.36-22.35 dB gain margin.Strong post-layout simulation result; not a silicon measurement.
Recovered post-layout line-regulation sweep from 3 V to 5 V across report-labelled process and temperature corners.
Post-layout line-regulation sweepThe worst visible curve rises by about 12.5 mV, so the base target is not closed.
Recovered post-layout dropout sweep with a 1.782 V output threshold and corner-dependent input-voltage markers.
Post-layout dropout sweepThe report summarizes approximately 126 mV dropout; raw post-layout data and verified load/corner mapping are not in the recovered package.
04 · Layout

Layout and physical verification

Layout

Present

Top-level integration is preserved in the archive.

LVS

CORRECT

Recovered comparison shows schematic-layout connectivity agreement.

PEX

Generated with warnings

Extraction and post-layout plots are present; warnings remain.

DRC

1007 results

1007 results in 8 of 423 checks; not DRC-clean sign-off.
Cadence top-level layout view for the team LDO project.
Top-level layoutArchived team layout; no tapeout or manufacturability claim.
Calibre LVS comparison window for the team LDO project showing a CORRECT result.
LVS comparison · CORRECTSchematic-layout connectivity matches; DRC remains unresolved.
Cadence post-layout STB simulation for the team LDO project.
Post-layout STBPost-layout simulation, not a silicon measurement.

Archive status

Front-end states survive; the post-layout hand-off is incomplete.

  • The primary archive retains the design library, ADE/Spectre states, and eight named testbenches.
  • The nested submission archive is truncated.
  • Plots survive, but the extracted netlist and full raw result database do not.
05 · Regional hardware

25 V-to-12 V semi-discrete regulator

The regional final was a separate hardware task: BJT characterization, component selection, assembly, and debugging of a semi-discrete feedback regulator. It was not post-silicon testing of the CMOS LDO.

  1. 01

    Characterize TIP42C/TIP32C and BD139/BD135 candidate BJTs

  2. 02

    Select and match devices; calculate feedback and compensation values

  3. 03

    Assemble and debug a 25 V-to-12 V semi-discrete feedback LDO

  4. 04

    Evaluate regulation, dropout, stability, load transient, and thermal behavior

06 · Test preparation

Automated-test preparation

For the national stage, I prepared a LabVIEW/IECUBE test architecture for PWS, DIO, DMM, and waveform resources. The design separates DUT settings from the interface and keeps a safe shutdown path for success, abort, and error.

  1. 01Initialize safely

    Open sessions, validate limits, and keep all outputs disabled.

  2. 02Set the operating point

    Apply VIN and load through a configurable DUT map.

  3. 03Measure

    Acquire actual voltage, current, and waveform data after settling.

  4. 04Calculate and save

    Store raw points, worst cases, units, limits, and validity together.

  5. 05Shut down

    Return the load to safety, turn VIN off, discharge, and close sessions.

Measurement rule

Keep every raw sweep point, calculate the worst valid case, and return results below the instrument floor as invalid or indeterminate—not as passes. The archived work is preparation, not a completed hardware PASS/FAIL dataset.

07 · Scope

How I present this project

This project shows selected contributions within a team analog-IC workflow: circuit reading, simulation, layout/Calibre practice, post-layout analysis, regional hardware debugging, and test-system preparation.

It does not claim independent LDO ownership, DRC-clean sign-off, tapeout, fabrication, post-silicon validation, a complete PEX rerun package, or a finished LabVIEW hardware-validation system.