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Third-author research / Published 2026

Numerical Investigation of Short-Channel Effects and RF Performance in Top-Gate In2O3 Thin-Film Transistors

A third-author contribution to a two-dimensional TCAD study of short-channel and RF scaling in top-gate In2O3 thin-film transistors.

Published in
Micromachines 17(5), 567
Role
Third author
Authors
Hanbo Xu, Mingyang Zhu, Zeen Fang, and Lei Zhang
Research communication

Academic poster

Academic research poster summarizing the top-gate indium oxide TFT scaling study with the calibrated numerical platform, published short-channel and RF figures, reported metrics, and scope
Academic research posterA 4:3 research poster combining exact paper metadata, the calibrated numerical platform, published figures, reported results, and an explicit numerical-only boundary for a modeled top-gate platform that is not experimentally validated here.Published figures + AI-assisted concept schematic · no new data
Two-panel simulated cutoff and maximum oscillation frequency scaling plots for top-gate indium oxide TFTs
Published figureFigure 12. Relationship of fT and fmax versus inverse gate length for top-gate In2O3 FETs. From Xu et al., Micromachines 2026, 17, 567. Licensed under CC BY 4.0.CC BY 4.0
Study results at a glancePublished paper-level values
~100 nm

Reported transition region

Numerical long-channel to short-channel transition in gate length.

124.32 GHz

Simulated fT at 20 nm

Extracted from the study's simplified small-signal framework.

157.64 GHz

Simulated fmax at 20 nm

A numerical result, not a fabricated-device measurement.

01

Problem

Ultrathin In2O3 is promising for high-current and high-frequency electronics, but aggressive lateral scaling makes short-channel behavior increasingly important. A systematic view was needed of how gate length changes threshold behavior, transconductance, and RF figures of merit in a top-gate device architecture.

02

Approach

The paper uses two-dimensional Silvaco Atlas simulation for a top-gate In2O3 TFT with a 1.5 nm channel and 7 nm HfO2 dielectric across gate lengths from 20 to 700 nm. Effective material and interface parameters are calibrated against a previously reported back-gate experimental device, then transferred to the independently constructed top-gate simulation platform.

The numerical analysis connects DC characteristics, DIBL, transconductance, lateral electric field, field-dependent mobility, and a simplified small-signal RF equivalent circuit.

03

Reported results

The study identifies a numerical transition near a 100 nm gate length. For gate lengths at or below 100 nm, it reports a negative threshold-voltage shift and DIBL rising to approximately 130 mV/V, together with non-classical transconductance scaling linked to a crossover between field-assisted transport and gate-controlled channel modulation.

At 20 nm gate length, the simulation reports fT = 124.32 GHz and fmax = 157.64 GHz. The paper also reports a less distinct transition in fT scaling than classical long-channel expectations and multiple fmax scaling regimes shaped by capacitance, transport enhancement, and short-channel non-idealities.

04

Scope and next steps

The highlighted trends are study-level numerical results; the modeled top-gate platform is not experimentally validated here. Tunneling, self-heating, substrate effects, and additional extrinsic parasitics remain outside the current drift-diffusion and simplified intrinsic RF framework.